In telecommunications transmission systems, there arises sometimes a need to store information from a transmitter because the receiver is busy. The information, however, must be recovered from storage in the same order in which transmitted. This process is known as first-in, first-out (FIFO).
In U.S. Pat. No. 3,979,733 granted Sept. 7, 1976 to Mr. A. G. Fraser, there was disclosed a FIFO queue. A read register, in the aforesaid Fraser patent, has recorded therein the address of the next memory cell to be read. Likewise, a write register has recorded therein the address of the next memory cell available for storing data. A comparison of the read and write registers indicates whether the memory cells are all full, all empty or partially empty.
It is frequently desired to use a FIFO queue as a communication path between a data producing process and a separate data consuming process. These processes are typically independent of one another and may not even be controlled from a common clock source. That is, the two processes may be asynchronous with respect to one another. The path carries messages from the data producing process to the data consuming process and it is frequently required to guarantee that the consuming process obtain only complete messages.
A problem arises if the data producing process has to abandon a message after inserting some of it into the FIFO queue. In that case, the consuming process may already have started the message. This situation arises, for example, when the data producing process is a transmission line with error detection equipment and the consuming process is a computer. If an error is detected partially through an arriving message, it is usually desired that the message be discarded and not processed by the computer.
In the aforesaid Fraser patent, however, there is no way of knowing when a complete message has been received. In the absence of such knowledge it is common practice to use two memories. The first memory is used to assemble one complete message at a time. The second memory is used to operate as a FIFO system in which the unit of storage is a message. Such an arrangement usually requires high speed processing circuitry which then becomes a bottleneck limiting throughput. Further, because two memories are used, circuitry is necessarily duplicated.